Synchronization schemes based on two flip-flops are well-known in art. Therein, two flip-flops are connected in series and are driven by a common clock signal.
The introduction of the second flip-flop aims to block a potential “metastable” condition of the first flip-flop. A “metastable” condition of a flip-flop may be caused by the asynchronous incoming signal changing its state exactly when the clock signal is changing. This condition leads to an unknown and unwanted situation in the output of the flip-flop. The standard technique is to introduce an extra flip-flop in order to block the “metastable” signal until the very next clock edge.
In some applications, mainly in the area of medical, automotive and space, a third flip-flop is used in the series behind the second flip-flop in order to increase the safety margin.
The above techniques are considered standard and safe. However, they introduce an inherent delay which is determined by the period of the clock signal which drives the flip-flops.
The present document addresses the above mentioned shortcomings of the standard synchronizer circuits. In particular, the present document describes synchronizer circuits which improve the inherent latency and/or improve the safety of synchronizer circuits without compromising the latency.